In DRAMs (Dynamic Random Access Memory) of recent years, a synchronous type that operates in synchronization with a clock signal has become mainly used. A frequency of the clock signal used for the synchronous DRAM increases year by year. However, in a DRAM core, a precharge operation, a sense operation, and the like are needed, and thus, it is not possible to increase the speed in proportion to a clock frequency. Accordingly, in the synchronous DRAM, a prefetch circuit is arranged between the DRAM core and input/output terminals to perform a parallel-serial conversion in the prefetch circuit. Thereby, an apparent high-speed operation is achieved (see Japanese Patent Applications Laid-open Nos. 2004-164769, 2004-310989, 2004-133961, 2003-272382, and 2004-310918).
For example, in a DDR2 synchronous DRAM, a 4-bit prefetch is performed in the prefetch circuit, and in a DDR3 synchronous DRAM, an 8-bit prefetch is performed in the prefetch circuit. Thereby, a high data transfer rate is achieved externally.
More specifically, in the DDR3 synchronous DRAM, 8-bit data is read at once from the DRAM core at the time of reading, and after the 8-bit data is temporarily stored in the prefetch circuit, the data is burst-outputted to outside. On the contrary, at the time of writing, the 8-bit data burst-inputted from outside is temporarily stored in the prefetch circuit, and thereafter, the 8-bit data is written into the DRAM core at once. To perform such operations, in the synchronous DRAM, a prefetch number is basically defined as a minimum burst length.
However, to realize a faster data transfer rate, it is inevitably necessary to increase the prefetch number. Thus, when the prefetch number is defined as the minimum burst length, it becomes impossible to be compatible with a conventional synchronous DRAM. In the case of the DDR3 synchronous DRAM, when the minimum burst length is set to 8, an operation at the burst length=4 which is possible in the DDR2 synchronous DRAM cannot be performed. As a result, the compatibility is lost.
To solve such a problem, so called a burst chop function has been proposed. The burst chop function is to make a designation in advance so that a burst operation stops in the middle at the time of issuing a read command or a write command. Accordingly, when a case in which the burst chop function is installed in the DDR3 synchronous DRAM is assumed, by the designation at the time of issuing the read command and the write command, it becomes possible to use a burst length=8 as a burst length=4. Thereby, even when the prefetch number increases, it becomes possible to be compatible with the past product (DDR2).
However, the burst chop function is, after all, to stop the burst operation in the middle. Thus, an input cycle of the command cannot be shortened. That is, in the DDR3 synchronous DRAM of which prefetch number is 8 bits, it is possible to receive the command by each 4 clock cycles (tCCD=4), while at the time of the burst chop, an input/output operation is completed in the first-half 2 clock cycles, and the last-half 2 clock cycles are a waiting time. That is, even when the burst length is shortened to 4 bits by using the burst chop function, the input cycle of the command is thereby not automatically shortened to 2 clock cycles (tCCD=2), and the input cycle of the command is still 4 clock cycles. Thus, there is a problem in that when the burst chop is performed, a data transfer efficiency is deteriorated.
As a method for solving such a problem, it can be possible to employ a method in which two sets of command decoders or address counters are arranged and the both components are operated with a delay of 2 clock cycles. However, in this method, the number of column address wirings and data buses are doubled, and thus, a chip area increases greatly. For example, when a chip in which data inputted and outputted simultaneously is 16 bits (×16 product) is assumed, if the prefetch number is 8, the number of data buses is 128 (=16×8) in a normal chip while two sets of 128 data buses, that is, as many as 256 data buses, are needed in the chip described above.
Further, in this method, when the burst length=8 is set, it is sufficient that only one of the circuits is operated. However, when the burst length=4 is set, it is necessary that the both circuits are operated. Thus, when the burst length=4 is set, a charge or discharge current of the data bus or the like is doubled as compared to a case of the burst length=8. As a result, there is a problem in that power consumption increases.